Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Silicon Labs/SiM3_NRND/SIM3L168_A/LCD_0/CLKCONTROL#0x0
RTCCLKDIV=DIVIDE_BY_1
Clock Control
Clock Divider.
RTC Input Clock Divider.
0 (DIVIDE_BY_1): undefined
1 (DIVIDE_BY_2): undefined
2 (DIVIDE_BY_4): undefined
3 (DIVIDE_BY_8): undefined
https://github.com/cmsis-svd/cmsis-svd-data